ericmtzr
Occasional Contributor
4 years agoMigrating Intel PSG Cyclone V GX to Agelix F
Hi,
My customer is Migrating Intel PSG Cyclone V GX to Agelix F and running into the following compilation error:
Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device
Compiler bug? It doesn’t make any difference what Agilex F-tile device I use and I don’t have any location constraints in the qsf file. You will see the compiler attempt to connect the F-Tile to all possible locations and fail.
The Platform designer file you need to check is called cv_pcie_dma_rxtx.qsys
The connections between my DMA and the Pcie isnt right yet but it should compile.