Forum Discussion
Memory Support with A5ED065BB32AI4S Agilex5 FPGA
Jay
For the A5ED065BB32AI4S (Agilex 5 E-Series SoC), the HPS EMIF cannot be placed in arbitrary banks such as 2A/2B/3A/3B.
The HPS DDR interface uses dedicated EMIF resources hard-wired to specific HSIO banks located adjacent to the HPS block.
Please check the following link for HPS subsystem and bridge system interation.
https://docs.altera.com/r/docs/817467/26.1/external-memory-interfaces-emif-ip-user-guide-agilextm-5-fpgas-and-socs/agilextm-5-emif-ip-for-hard-processor-subsystem-hps
Hi,
Thanks for your reply .
For PL X32+ECC with the 2A,X32+ECC with the 2B bank.
For PS X32+ECC with the 3A,X32+ECC with the 3B bank .
is the above mapping fine?
Thanks
Jay
- yoichiK_altera1 month ago
Contributor
Hi Jay
Please see my comments here
For PL X32+ECC with the 2A,X32+ECC with the 2B bank. --> yes.
For PS X32+ECC with the 3A,X32+ECC with the 3B bank . -->No, If only one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE. (Bank 3A.)
- jaykrishna11 month ago
New Contributor
Hi,
For PS X32+ECC with the 3A,X32+ECC with the 3B bank . -->No, If only one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE. (Bank 3A.)----.> As we have 1GB DDR4 and we need 4GB so which bank can use ?
mapped 2GB with the Bank 3A and other 2GB where can map?
Thanks
Jay
- yoichiK_altera1 month ago
Contributor
You can use 3A bank for 4GB DDR4. You can not share memory across 3A band and other bank. 4GB DDR4 is dedicated memory for HPS EMIF.