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jaykrishna1's avatar
jaykrishna1
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3 days ago

Memory Support with A5ED065BB32AI4S Agilex5 FPGA

Hi, I am using the A5ED065BB32AI4S FPGA, Want to connect the DDR4 X32+ECC with the 2A,2B,3A,3B. We have 512M X16 memory want to interface 4GB with the PS and 4GB with the PL how i can ? Thanks Ja...
Core Logic
yoichiK_altera's avatar
yoichiK_altera
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1 day ago

Jay

 

For the A5ED065BB32AI4S (Agilex 5 E-Series SoC), the HPS EMIF cannot be placed in arbitrary banks such as 2A/2B/3A/3B.

The HPS DDR interface uses dedicated EMIF resources hard-wired to specific HSIO banks located adjacent to the HPS block.

Please check the following link for HPS subsystem and bridge system interation.

 

 

https://docs.altera.com/r/docs/817467/26.1/external-memory-interfaces-emif-ip-user-guide-agilextm-5-fpgas-and-socs/agilextm-5-emif-ip-for-hard-processor-subsystem-hps

 

https://docs.altera.com/r/docs/814346/26.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/bridges-system-integration

jaykrishna1's avatar
jaykrishna1
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1 day ago

Hi,

Thanks for your reply .

For PL X32+ECC with the 2A,X32+ECC with the 2B bank.

For PS X32+ECC with the 3A,X32+ECC with the 3B bank .

is the above mapping fine?

Thanks

Jay