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Altera_Forum's avatar
Altera_Forum
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14 years ago

Memory required to compile 128k sample depth on SignalTap II Logic

I'm attempting to compile a project in SignalTap II Logic in Quartus II 11.0 that will have 128k sample depth. I am using an Altera Stratix III DSP Development Kit. I can only compile the project up to 16k. I assumed if I can interface the DDR2 SDRAM, then I'll have the necessary memory, but now I'm not so sure anymore. Can anyone tell me if I need the DDR2 SDRAM to get 128k sample depth and if not, what type of memory or add-on do I need for this type of board in particular?

Daniel

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The amount of memory used by Signal tap is the internal block rams of the device, so it will not use the DDR2 DRAM to extend the sample depth. So the number of block rams required is dependent upon the number of signals you are tracing, and the number of block rams available in the device.

    If you really desire to capture that many samples, it may be better to either, build your own capture/playback hardware/software that uses the DDR2, or hook the signals in question to a mictor connector or some similar connector and use and external logic analyzer to capture the data.

    Pete