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Altera_Forum
Honored Contributor
15 years agoMemory bit not enough for Stratix II EP2S60F672C3
Hi All, I'm designing specialized RAM for my project and is prototype on Stratix II, EP2S60F672C3. Below is my design module ram (datain, address, we, clk, dataout); //parameters para...
Altera_Forum
Honored Contributor
15 years agoYou misunderstand the error message. It's about your PC being "Out of memory" during compilation, not FPGA memory. Assuming your PC has more than 2 GB RAM, then it's a problem of 32 Bit Windows settings. There's an option to enable one more GB for the application, it has been discussed in the forum, and is also mentionend somewhere in a Quartus readme file.
It's also a fact, that "Out of memory" sometimes can be triggered by "impossible" designs, e.g. involding infinite iterations. But your design seems fine. The "Out of memory" problem has to do with complexity of the used design and FPGA size. To check your design first, you can compile it without specifying a particular FPGA type.