Memory bit not enough for Stratix II EP2S60F672C3

Hi All,

I'm designing specialized RAM for my project and is prototype on Stratix II, EP2S60F672C3. Below is my design

module ram (datain, address, we, clk, dataout);

//parameters

parameter row = 4;

parameter column = 4;

parameter data_width = 4;

parameter address_width = (row+column);

//input

input [data_width-1:0] datain;

input [address_width-1:0] address;

input clk;

input we;

//output

output [data_width-1:0] dataout;

//register

reg [data_width-1:0] ram[2**address_width-1:0];

reg [data_width-1:0] dataout;

//behavior descryption

always @(posedge clk)

begin

if (we) //write operation

ram[address] <= datain;

end

always @ (negedge clk)

begin

dataout <= ram[address]; //read operation

end

endmodule

According to my calculation, the memory usage should calculated as below

Memory usage :# address location *# bit in each location

case 1: DATA_WIDTH = 4;

memory usage = (2^8) * (4) = 1024 bits;

case 2: DATA_WIDTH = 36;

memory usage = (2^8) * (36) = 9,216 bits;

but my design would require 1296 bits to store big number, so...

case 3: DATA_WIDTH = 1296;

memory usage = (2^8) * (1296) = 331,776 bits;

Stratix II EP2S60F672C3 has 2,544,192 bits, by right my design can be fit into this device. However, i got an error:

"error: out of memory in module quartus_map (2147 megabytes used)"

Anyone has any idea why my design is using up 2147Mb?

Thanks in advance,

ty6