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Altera_Forum's avatar
Altera_Forum
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13 years ago

Memory array to pio using DMA (Video)

Hi, all!

I need to create a videosystem with soft processing on Nios II. Hardware: Camera MT9P001 (TRDB-D5M), Board DE2-115 (Cyclone 4, Video DAC ADV7123, SRAM 2 MB).

System structure:

Camera (MT9P001) -> Hardware preprocessing-> SRAM -> Soft processing ->[ Video DAC for test result]

I have developed a SOPC with DMA (Mem-Mem, Mem-PIO, PIO-Mem), alt_pll for video clock. At first i'm testing video out.

Question. How to generate synchronous transfer of data by means of DMA (I need a signal such as Data Valid)?

Where I can found a waveform of DMA-transfer (Memory->PIO)?

May be it is wrong way, and it is impossible to generate a synchronous transfer from Memory to PIO?

top level:

nios DUT(

.clk_0 (CLOCK_50),

.clk_VGA (CLOCK_39), // Clock from PLL to VGA controller

.out_port_from_the_VGA_data ( // Colour to VGA Controller

{VGA_B_from_cpu[7:0],

VGA_G_from_cpu[7:0],

VGA_R_from_cpu[7:0]}),

...

);

In SOPC clock CLOCK_39 connect to PIO (VGA_data) and DMA.

Thank you.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes a DMA can do what you are looking for. But I don't recommend using a PIO to send video offchip. You can't predict the rate at which the DMA will write pixels to the PIO. Instead have the DMA write pixels into a FIFO that has the read port sampled at a fixed rate so that the DAC will see a constant stream of pixels.

    I think if you ripped the stuff out of this design at the end of the pixel pipeline, exported a FIFO interface, and connected that exported FIFO interface to your ADC it should work. Just change the C code for whatever buffer size you use in your design. If you use Qsys then exporting a FIFO is easy, you just click the export as column. In SOPC Builder you would need to create a custom FIFO, with one side connected to the DMA and the other side exported through a conduit.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes a DMA can do what you are looking for. But I don't recommend using a PIO to send video offchip.

    --- Quote Start ---

    You can't predict the rate at which the DMA will write pixels to the PIO.

    --- Quote End ---

    I am afraid this.

    --- Quote Start ---

    Instead have the DMA write pixels into a FIFO that has the read port sampled at a fixed rate so that the DAC will see a constant stream of pixels.

    --- Quote End ---

    i.e. i need in "Avalon-MM Write Slave to Avalon-MM Read Slave" configuration of FIFO?

    i.e. SOPC with inegrated VGA- controller can be realized as:

    (<sram>-Avalon MM-TS)->

    (Avalon MM TM-<bridge to sram>-Avalon MM S )->

    (Avalon MM M-<dma controller>-Avalon MM M)->

    (Avalon MM S-<fifo>-Avalon MM S )->

    (Avalon MM M-<my_master>-Avalon Conduit )

    where MY_MASTER has a clock source calculated for video out, and not equal clock for any master (Nios).

    I think, I'm right:) Thank you, BadOmen!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Some DMAs support streaming directly so sometimes you don't even need the FIFO since DMAs have FIFOs inside them. Using SOPC Builder you still need a dummy component in order to get the FIFO/DMA interface up to the top using a conduit. If you used Qsys you could export the ST port of the DMA directly and wire it up to your DAC.

    By the way I forgot to copy the link to the design I was talking about... http://www.alterawiki.com/wiki/modular_sgdma_video_frame_buffer
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    thank you for your project. I've seen it before. I didn't want to use the ST-protocol.

    If I correctly understand arbiter logic in SOPC, DMA transfer will be paused after transfer 1024 (maximum in my SOPC) word. In that case, DMA can't be use for video out to DAC directly.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    That's correct, the standard DMA will stop after the transfer is complete and so in order to avoid underflowing you would need to have it operate faster than the DAC rate and ensure there is enough buffering to compensate for the time taken to get the DMA started again. Typically you use something like the scatter-gather DMA that can coordinate multiple frame transfers without software intervention.

    In that design I pointed you at this is all taken care of in the hardware. The video frame descriptors are tagged with a 'park' bit which means the same frame keeps getting displayed until you provide another frame. So you would just connect the ST data up to your DAC, hardcode the ST ready signal high, leave the valid signal as a no-connect, and use your DAC clock to clock the mSGMDA (or put a clock crossing FIFO in between if you want the DAC and mSGDMA domains to be different).