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Altera_Forum's avatar
Altera_Forum
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14 years ago

Memory Allocation With QSys

Hi Guys,

I'm stuck at the moment with being able to find and use enough memory. I need advice how to rearrange the memory so i can get a video frame buffer (like a DCFIFO or 2port RAM). I'll ask a quick question for thos skimming and later if you read on I'll explain what i thought of and why i'm stuck.

short question: if a nios core and the qsys controls my sdram, how can i take some of this ram to use as a buffer for memory?

___________________________________________________________

details

hardware: A terasic DE2-115. Has 128mb RAM and 2MB of SDRAM and 8Mb flash.

memory requirements

nios ethernet program: Apparently 630Kb

video frame buffer: For 800x600 24bit RGB pixel data. This buffer is to be between the pixel feed of 50MHz and the VGA out of 40MHz. SO it would need to be atleast 1/5th of a frame big yeah?

problems:

nios won't work unless it has the sdram: For some ****en reason the Nios won't run on the SRAM and will only run when it has the SDRAM. This means the program of 1mb is consumming all my SDRAM.

As brought up by someone else in http://alteraforums.com/forum/showthread.php?t=31636&highlight=using+sram+to+run+nios+program

options:

move nios to sram: Won't work as stated above. elf fails to download.

make on-chip ram: The FPGA doesn't have enough memory blocks to make my current program and any shred of a buffer.

make video buffer in the sram: Problem is SRAM has only 1 port, i can't think of a good way to control it like a dcfifo allowing simulataneous (or seamless) reading and writing.

flash for nios: Haven't tried but i'm going to assume the same problem as using the SRAM. Too slow for my application i would think? (gigabit ethernet)

Time is ticking and i have 5 days to finish this project and this is one of the last hurdles. Please Help!! Thanks in advance

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Nios should work, if SRAM is big enough. Also are You sure, that Your Nios program takes 1Mbyte (8Mbit), not 1Mbit?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    From what i can gather its about 630K (i assume thats in bits?). The 630K matches the reports i go from Nios when i delibrately short changed it to see what error i would get.

    From the forum trolling i've been doing I have a feeling that the Terasic SRAM SOPC componenet isn't quite right. I'm going to try figure out how to use a generic component for the SRAM in SOPC and see if that works. I'll do it all in a "babies first Nios build", so to eliminate any question size?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did You set optimization to -Os ? It shows the binary size after successful compilation in bytes.

    E.g. my Nios project compilation report shows:

    Info: (project.elf) 221 KBytes program size (code + initialized data).

    Info: 794 KBytes free for stack + heap.

    I have 8MB SDRAM chip, but I've edited linker script to exclude only 0x00800000 - 0x00900000 space and leave the other free for my own buffer. The whole memory takes addresses 0x00800000 - 0x00ffffff in SOPC.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Nice trick thanks. Its 605KB (bytes).

    I've attempted to make my own tri-state controller and bridge in QSys; but this has failed. I have posted details in this topic specific to this

    http://www.alteraforum.com/forum/showthread.php?p=133879#post133879

    I don't think i could split my SDRAm though, wouldn't that bring alot of timing issues sharing the bus separately like that. The reason i need the SDRAM is for a video buffer so that would dominate the BUS would it not; causin problems for my ethernet?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The avalon bus is fully synchronous and has wait signals for data delay if access is granted for other master during that time, so no problems there at all.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    How exactly is your Qsys set up to do that. I understand that you have modified the offset in the script somehow.

    Do you have two Sdram control modules? Or are they custom objects or am I way off?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Difference between QSys and SOPC is the wait signal which changed behavior.

    As long as you use QSys masters, nothing to change, but if it's custom masters, you need to ask for transactions independent of waitrequest.

    An issue for multi master access is the address switch overhead that might kill your bandwidth.

    it would need bursting in SOPC, while the advantage on QSys is that now bursting became seamless : Right click on MM-Slave and tick "Show arbitration shares", and change the "1" "1" round robin to a value depending on your fifos size "16" or "32".

    You can also add a bridge to the NIOS master access so that as long as NIOS do not access the buffers memory, it would not disturb when accessing its other peripherals, thus implementing data and instruction cash would be good.

    Yet the SRAM has to work, I just got a DE2-115, I'll keep you updated when I manage with SRAM working with QSys.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    post edit --- got it working for a de2-115

    @wass and others

    With a fresh head i had another go and matched some of the unknown parameters with the Terasic TCL. I have now created a successful tristate controller and bridge to allow the nios to run on SRAM. note the original problem is obviously the terasic part. i have a feeling because it may use the old sopc tri-state set up and hence the problems with qsys. i'm guessing though.

    how to get it working

    I have attached a zip file with the images you'll need, showing the settings and connections.

    you'll see the timing is actually more conservative than the sram datasheet says. i imagine that it could be improved and its possible that my set up isn't using one of the tighter running modes of the ram; but it works.

    1. Make a "Generic Tri-state controller". Match all the settings to the screen shots in the attached zip.

    2. Insert a "tri-state conduit bridge".

    3. Connect the two together.

    4. Connect the Avalon MM slave of the controller to you CPU data and instruction masters.

    5. Connect clocks and resets.

    6. Set you Nios in QSys to use the Tri controller for reset and exception vectors.

    7. In Nios EDS, edit your BSP settings on the linker page to use the tristate controller.

    8. Connect the top level signals as per the code quote below. Note that i swizzled the Byte enable bits together. i assume this is correct, but maybe not since it appears their use is optional? (this works)

    9. There ya have it, my dodgy SRAM. 

      // SRAM - Using Tristate Bridge
   .sram_tcm_address_out        (SRAM_ADDR),          // sram.tcm_address_out
   .sram_tcm_outputenable_n_out (SRAM_OE_N),      //   .tcm_outputenable_n_out
   .sram_tcm_byteenable_n_out   ({SRAM_UB_N,SRAM_LB_N}),  //     .tcm_byteenable_n_out
   .sram_tcm_read_n_out         (),              //     .tcm_read_n_out
   .sram_tcm_write_n_out        (SRAM_WE_N),          //     .tcm_write_n_out
   .sram_tcm_data_out           (SRAM_DQ),             //     .tcm_data_out
   .sram_tcm_chipselect_n_out   (SRAM_CE_N),        //     .tcm_chipselect_n_out

    Thanks to Socrates and BadOmen for their advice.

    Onto the next challenge for me.