Honored Contributor
Honored ContributorDifference between QSys and SOPC is the wait signal which changed behavior.
As long as you use QSys masters, nothing to change, but if it's custom masters, you need to ask for transactions independent of waitrequest. An issue for multi master access is the address switch overhead that might kill your bandwidth. it would need bursting in SOPC, while the advantage on QSys is that now bursting became seamless : Right click on MM-Slave and tick "Show arbitration shares", and change the "1" "1" round robin to a value depending on your fifos size "16" or "32". You can also add a bridge to the NIOS master access so that as long as NIOS do not access the buffers memory, it would not disturb when accessing its other peripherals, thus implementing data and instruction cash would be good. Yet the SRAM has to work, I just got a DE2-115, I'll keep you updated when I manage with SRAM working with QSys.
