Megafunction altparallel_flash_loader--what is this

In my work, I plan to use two flash to store the data sheet, which are two seperate data sheet. In the same clock cycle, FPGA can get the two flash data. Actually speaking, the data sheet are all 16bit data-width , so with two 16bit data-width flash , I can get 32 bit data-width at the same time.

When I add "cfi_flash_0" and "cfi_flash_1" into SOPC ,both of them link to "tristate_master" , then can I control the two flash seperately when I write them and read them at the same time ? they all link to "tristate_master" !

Hope for your reply!

Thanks very much!