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Honored Contributor
Honored ContributorMega Wizard dual Clock FIFO Strange behavior !!!!!
Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and ...
Altera_ForumHonored Contributor
Honored Contributorhave you somehow connected some of the data bits back to the output enable. Can you trace the paths on the PCB?
Without all the info, I can only guess whats wrong. It is definitely a design issue.
