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Honored Contributor
Honored ContributorMega Wizard dual Clock FIFO Strange behavior !!!!!
Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Also, you realise your design only ever writes a single word to the FIFO? --- Quote End --- The rd_en and rd_clk come from the external microcontroller , the tri-state are there because in the full design the microcontroller would read and write to different FIFOs , but when i noticed this problem , i simplified the design just to help solve it . The design meets the timing constraints . U see the value that I write to the FIFO is (out_D<="0000111111111111"; ) or 0x0FFF in hex , the design is working fine with this value , but the problem is that if u just only change this value to 0xFFFF the operation screws !!!!!! , and again just changing this value to say 0x00FF the design works well again !!!!!!
