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Honored Contributor
Honored ContributorMega Wizard dual Clock FIFO Strange behavior !!!!!
Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and ...
Altera_ForumHonored Contributor
Honored ContributorWHy do you have a lot of tri-states? they are only driving an out pin?
where does the rdclk and rden come from? what state is your state machine in when it "doesnt work"? does the design meet timing?
