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Altera_Forum
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8 years ago

Mega Wizard dual Clock FIFO Strange behavior !!!!!

Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The DCFIFO is a very old and very well tested IP, so I can only assume there is a problem with your design. the data path has no link to the control path at all, so your problems are impossible. The only issue can be a design issue.

Can you post the code ? or the project?