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Honored Contributor
Honored ContributorMega Wizard dual Clock FIFO Strange behavior !!!!!
Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Not really a lot of detail - are you sure write enable is low? are write enable and read enable are synchronised with the correct clocks? Are you sure the read enable is even asserted? --- Quote End --- Every thing is working fine man , I can fill and empty the FIFO correctly , for example if I fill the FIFO with 0x00FF it works fine , but when I use values like 0xFFFF , it becomes a mess . The test bench I wrote for the design is giving correct results no matter what values are used , so the operation is verified. The problem only occur in practice . I know its a pretty confusing problem , but I still can not find explanation !!!!
