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Altera_Forum's avatar
Altera_Forum
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10 years ago

Mega Function RAM I/O Data Bus

I'm trying to implement a memory buffer between microcontroller and EP3C16 . I'm using Mega function to generate the RAM memory. The problem is that it generates separate input and output data bus. I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The FPGA's internal RAM can only be generated with separate input and output buses. You can't generate one with a bi-directional data bus.

You'll have to wrap your RAM with some logic that determines when to: a) read the RAM's output bus and drive it to the Micro and b) when to tri-state the FPGA's pins and drive the data received from the Micro into the RAM via the input bus.

Cheers,

Alex