Forum Discussion

kgupt8's avatar
kgupt8
Icon for New Contributor rankNew Contributor
6 years ago

Meeting hold time in Cyclone V Configuration with Micron Flash

I am using Cyclone V GX FPGA. Using ASx1 Interface to configure the FPGA through 128Mb Micron Flash. We just realized that Cyclone V in errata specifies min HOLD Time of 2.9ns on its AS_DATA1 pin. Si...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Unfortunately there is no way to make the changes in delay on the pin as this is a dedicated pin. You will need to modify your board in order to meet the specification