meaning of transport delay

Here is wiki statement on delta delay and similar statements seen in many other resources:

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In vhdl (http://en.wikipedia.org/wiki/vhdl) simulations, all signal assignments occur with some infinitesimal delay, known as delta delay. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond(fs).

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this is an example of how it can cause problems:

a <= b; -- comb. statement

one may think that in functional simulation it means (a) is wired to (b) and hence if (b) changes from 0 to 1 so would (a) with zero delay(concurrent).

but try it and use a clock to sample both (a) & (b),keep changing clock phase and you will get at some point a strange result. clock samples (a) as 0 but (b) as 1

The solution is to generate all signals from a reference signal e.g. clock...etc.

if we make (b) the reference then:

b1 <= b;

a <= b;

thus (b1) & (a) will have no delta delay.