meaning of transport delay

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Delta delay is not a 'simulation bug' is in no way dependant on 'simulator resolution' and is not 'too small to be visible' (open a list window and see for yourself).

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No certainly it is not a bug per se but I amplified the expression to convey that it got nothing to do with design. I know for sure it depends on update rate and hence I thought it will depend on resolution(step). As to visibility, I mean on the waveforms... are we talking about same thing?

Good to see your comments here as it stimulates further research.

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the 'after' keyword does not imply inertial delay. Rather it is the lack of the word 'transport' that implies inertial delay.

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Just different wording of same concept. Naturally I mean by after as after on its own.

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Actually it would be 'wait until rising_edge(clk)'...but regardless, waiting on a signal is not an assignment statement therefore it is not an 'inertial' or a 'transport' delay.

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again I am referring to clk edge, not actual syntax and I say "in effect" which means it is my personal perspective and certainly not that of simulator designers who will have their own intricate terminology.

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There is no continuous sampling going on. A 'transport' delay simply means that a previously scheduled transition on a signal will not be erased from the signal's queue of scheduled transitions when a new assignment comes along.

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Just different wording of same thing...the simulator tool is sampling(or not erasing) at start of every of its cycles, I don't mean sampling in the sense of a clk edge or ADC.

Thanks for the comments.