meaning of transport delay

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1) delta delay: In effect a simulation bug. Simualtors can assign a target not immediately(zero delay) but on its

next simulation cycle, hence it is dependant on simulator resolution and is usually too small to be visible but

may mystify beginners in verification.

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Delta delay is not a 'simulation bug' is in no way dependant on 'simulator resolution' and is not 'too small to be visible' (open a list window and see for yourself).

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2) default delay i.e. after statement in VHDL implies what is called inertial delay.

Here model ignores any signal transients that are shorter than delay time (samples it at end of given delay).

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the 'after' keyword does not imply inertial delay. Rather it is the lack of the word 'transport' that implies inertial delay.

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The wait for clk edge is in effect regular inertial delay(regular after).

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Actually it would be 'wait until rising_edge(clk)'...but regardless, waiting on a signal is not an assignment statement therefore it is not an 'inertial' or a 'transport' delay.

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3) transport delay: as 2 but transients are meant to pass through

(samples continuously but makes the target assignment after given delay)

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There is no continuous sampling going on. A 'transport' delay simply means that a previously scheduled transition on a signal will not be erased from the signal's queue of scheduled transitions when a new assignment comes along.

Kevin Jennings