meaning of transport delay

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I wonder anybody can explain me the meaning of transport delay and how differ from just (after) statement.

thanks

Pete

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Inertial delays (the default) can basically be overriden by a subsequent assignment. Transport delays are not. Consider the following possible model for a 10 ns delay line. You might model it like this...

 
process(Inp_Pin)
begin
  Out_Pin <= Inp_Pin after 10 ns;
end process;

The problem is that if Inp_Pin is a pulse that is shorter than 10 ns (the length of the delay) then you won't see anything come out on Out_Pin. For example,

Inp_Pin <= '0', '1' after 1 ns, '0' after 2 ns;

The first assignments of '0' (at t=0) will be overridden by the assignment of '1' (at t=1 ns) and that assignment will in turn be overridden by the assignment of '0' after 2 ns. By 'overridden' I simply mean that the result of the first assignment to 'Out_Pin' has not taken effect before there is a subsequent assignment so the result of that first assignment has basically been cancelled and forgotten.

However, the following code does accurately model a delay line. The response to the above mentioned 'Inp_Pin' will be the 'Inp_Pin' signal delayed by 10 ns;

 
process(Inp_Pin)
begin
  Out_Pin <= transport Inp_Pin after 10 ns;
end process;

Run a simulation so that you can see the differences. Since currently there are no products that synthesize a delay line from VHDL input 'transport' is ignored by synthesis tools. There aren't many other uses for 'transport' other than in delay lines (or similar constructs like a PCB trace model) so the main use for 'transport' you'll find is in a testbench...where it is quite handy, but even there not very frequently needed.

Kevin Jennings