meaning of transport delay

In simulation delay modelling is one of at least 3 types:

1) delta delay: In effect a simulation bug. Simualtors can assign a target not immediately(zero delay) but on its

next simulation cycle, hence it is dependant on simulator resolution and is usually too small to be visible but

may mystify beginners in verification.

2) default delay i.e. after statement in VHDL implies what is called inertial delay.

Here model ignores any signal transients that are shorter than delay time (samples it at end of given delay).

The wait for clk edge is in effect regular inertial delay(regular after).

3) transport delay: as 2 but transients are meant to pass through

(samples continuously but makes the target assignment after given delay)