Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

MaxV IO voltage compatibility

Hi everyone,

I am working on a MaxV design that needs IO compatibility with ICs that will be powered from 2.3V. Looking at the MaxV datasheet and the pin configurations in Quartus I am led to believe that the IO voltages can only be one of a finite number of voltages: 1.8V, 2.5V, 3.3V.

I am surprised that the MaxV devices would be so restrictive. Does anyone have any information as to whether it is truely required that the IO rail voltage be supplied as one of these small set of voltages? Again, I'd like to drive the VCCIO at 2.3V.

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi:

    Although you can run your IO at 2.3V, using the 2.5V settings, you will be out of spec. (Or at the low extreme of the spec). This would mean that although it will probably work, it really depends on what you are connected to. If the other device has CMOS inputs (VS LVTTL) and is also running on the 2.3 supply you are probably OK, but just de-rate your timing requirements a bit in your constraints.

    The timing models are for min/max voltage/ temp /process corners.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks for the reply. Do you have any insight as to what is different in the chip when the different voltages are selected? I read somewhere on one of these forums that the voltage selection had no effect on how the device was programmed and that the voltage setting was used by Quartus for calculations of power consumption, etc.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    With FPGA, the voltage settings are also used to translate current strength to output transistor selection.

    It's pretty obvious that most of the IO specifications are there to achieve compliance with nominal JEDEC voltage standards. I didn't check with MAX II and MAX V series, but I'm rather sure that similar to Cyclone FPGA, the IO cells will work over the full supported voltage range independent of Quartus settings.