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Altera_Forum
Honored Contributor
15 years agoMaxPlus 2: compiling errors
Hello everyone, i am berni69 and I'm studing telematics with our software, but like all the begginers in a new field, i have some mistake's programming in vhdl. For this reason the compiler show me e...
Altera_Forum
Honored Contributor
15 years agoThe error message isn't fully correct, because there is no else clause to the clock edge condition. Quartus gives a better understandable message.
--- Quote Start --- Error (10818): Can't infer register for "n[0]" at mod_tr.vhd(22) because it does not hold its value outside the clock edge --- Quote End --- The code can be compiled, when you change it like this:process (start,clk,clr)--contador
variable n: integer range 0 to 4;for the
begin
if clk'event and clk='1'then
n:=contador;
if start='1' or clr='1' then
n:=0;
elsif contador/=4 then
n:=n+1;
elsif contador=4 then
clr<='1';
end if;
contador <= n;
end if;
end process; You can write the same logic without the variable n. I don't think, that the code works as expected, because the signal clr is only set but never reset.