MAX/MIN DELAY CONSTRAINTS VS INPUT/OUTPUT DELAY

Question

Hi,I am new to timing analysis.Please help me to understand the difference b/w min/max delay constraints and input/output delay constraints.How to identify which constraints to be set for FPGA ports?

khaichein_y_intel · Answer

Hi,You may use set_input/output_delay constraints to specify any external device or board timing parameters and use the set_min/max_delay command to specify an absolute minimum delay for a given path.You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53018.pdf (7-24, 7-28) for details.Thanks.

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MAX/MIN DELAY CONSTRAINTS VS INPUT/OUTPUT DELAY

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