Altera_ForumHonored Contributor9 years agoMaximum Performance of DDR2 ALTMEMPHY on Cyclone-III Hi I have a design, using DDR2 and ALTMEMPHY on the Cyclone-III. My DDR2 IOs are on the side of FPGA (Row IO). According to the 2008 release of AN-445, maximum clock rate of the ALTMEMPHY is 16...Show More
Recent DiscussionsError (209014): CONF_DONE pin failed to go high in device 1.Implementation of lower data rate.eFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8