Maximum inputs per LAB

It's usually a bad idea to try to do manual location assignments, as you've discovered. Just let the Fitter do its thing. What are you trying to accomplish here?

I wouldn't be trying to do this if the Fitter were doing a good job.

A better solution is to first look at your timing constraints and timing reports. Can you post your .sdc file and the report on the path that is failing timing? Then based off of that, you make choices for optimizing the design, either flipping switches for how synthesis and the Fitter work or adjusting your HDL. Manual location assignments should be your absolute last resort.

Failing paths differ with every run. The one commonality is routing overload. The entire area where pipeline stages sit is bright red in the "routing hotspots" view. And it is difficult to optimize the design if you don't know the limitations of the hardware. If there is indeed an undocumented limit on the number of inputs per LAB, I could at least try to rework the algorithm to reflect that constraint.

Again, it would be most helpful to start with your timing constraints and to see the failing path report.

Right off the bat, I notice that you have over 0.5 ns of clock skew, which could potentially be high (I usually see it down at 100 ps or lower), and there is over 2 ns of delay on the launch clock path. Can you use a regional (quadrant) clock instead of one of the global clock resources? Regional clock resources have less skew and a smaller insertion delay.

Regional clocks are an interesting idea, I haven't even considered their effect ... I really don't want to put in clock-crossing logic at this point, but it's something to keep in mind in future.

Interesting. Turning off hold timing optimization somewhat eases the routing pressure, setup failures in this particular pipeline go away (at least at 180 MHz), but instead I see a bunch of hold failures elsewhere in the design.

With everything packed to maximize horizontal dependencies (everything manually assigned locations and every LUT dependent on the output from a register in a LAB immediately to the left of it), the most direct left-to-right links I see crossing a single boundary is 14. Not sure if that's a hard limit, however (the fitter is still somewhat reluctant to use them - most of the time it won't even use all 14, would route 10 or 11 directly, and send the rest via a Rx/Cx interconnect.)

A corollary. The handbook states that Cyclone V ALMs in shared arithmetic mode can do 3-input adds, with 2 output bits per ALM. However, that would require 6 inputs per ALM and 60 inputs per LAB. And, since there aren't enough feeds to supply all 60 inputs at once, the carry chain needs to be spread over multiple LABs. If you're adding three 32-bit numbers, you might naively expect to need 2 LABs for that (one full LAB and 6 out of 10 ALMs of the LAB immediately below). In practice, it's going to put bits 0..9 into the bottom half of LAB#1 (say, X78_Y6), bits 10..19 into the top half of LAB# 2 (X78_Y5), and bits 20..31 into LAB# 3 (x78_Y4). (Confirmed with Chip Planner. Conveniently, the carry chain is allowed to span only half of the LAB.)