maximum clock speed for cyclone iv

Look at Table 1–25. PLL Specifications for Cyclone IV Devices (p470)

http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf

The maximum for a PLL input is 472MHz. If you read on further, you will see that 433MHz is too fast for a GPIO pin.

Keep in mind that you could divide the external clock and then use a PLL internal to the FPGA to increase the clock frequency.

Cheers,

Dave

thanks a lot for your reply.

i have one more question: where did you see maximum pll input for GPIO pins? i couldn't see :)

does this also mean that we can not build a communication circuit with cyclone iv-e series?

actually, it is enough to create 250 mhz clock frequency for us. we can work with an appropriate anntenna.

thanks again.

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i have one more question: where did you see maximum pll input for GPIO pins? i couldn't see :)

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There's no such thing. There is either the "maximum PLL input frequency" (which I provided the page reference) and the "maximum GPIO frequency" which is further on in the document, and depends on whether you are using LVDS, HSTL, LVCMOS, etc, which you did not state, so I cannot provide a page reference.

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does this also mean that we can not build a communication circuit with cyclone iv-e series?

actually, it is enough to create 250 mhz clock frequency for us. we can work with an appropriate anntenna.

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You would generally have at least an ADC and DAC between an antenna and your FPGA, and those components define your FPGA interface requirements. For example, you might use JESD204 parts, which use SERDES, or you can use parts with LVDS interfaces, or LVCMOS interfaces ... without knowing what ADC/DAC you are using, you cannot select the FPGA.

Cheers,

Dave