Maximizing memory around a Stratix-IV

Thank you very much for the quick response, and on pointing me to the service request process!

I am comforted that there would be roughly enough pins for a 96-bit interface on the to and on the bottom, because 2x96 is the total width we need.

However with one of three 64-bit interfaces on the side, if I understand the speed table at the from of chapter 7 that interface would run much slower than the top/bottom interfaces;and thus too slow for this massive-bandwidth buffer (and we also wouldn't have enough pins for the RLDRAM on the sides).

But a 64-bit interface on each of the top and the bottom and a third 64-bit interface split between the top and the bottom would work, as would Top=64+32, Bottom=64+32, or 48+48, 48+48 (if there are enough address pins).

Also, at least Samsung makes DDR3 in a 64Mx16 die (K4B1G1646D). So ehat you are saying is that that still need x4 or x8 DQS/DQ groups... that explains a lot of the mystery by pointing out that there is an entire layer of pin grouping that I had not considered.

I will go and learn the next level, and when I have further questions of such detail, I will use the service request process.

Thanks again!

memory_monkey response:

Yes unfortunately the side banks have lower performance.

An Interface cannot generally be spread across the top and the bottom of the device, and core timing becomes an issue.

The x16 Samsung device you mention is indeed actually constructed of two x8 DQS groups, DQSL/DQSL# = DQL0-7 & DQSU/DQSU# = DQU0-7. Hence it is x8/x9 groups that you are actually counting/using.

You would need to do something like 64 & 32 in both the top and bottom banks, but I am not aware if 96bits of total data pins and two complete sets of CAC signals will fit, you would need to try this out for yourself.