Honored Contributor
Honored ContributorHi Max Mem,
Your getting confused between the "Total Memory Interface Width" and the "DQS/DQ Group Width". From your description, your optimum/easyest solution would be 3 64bit wide DDR3 Interfaces. DDR3 devices (doesn't really matter if they are 8 or 16bits wide themselves) are always either x4 mode or x8 only. Hence if the devices you are looking at are 16bit wide devices these are probably actually constructed of 2 x8 DQS groups. Put simply, every 8bits of data or DQ pins have a DQS/DQS# strobe pair of signals. Hence for DDR3 you should be counting the number of either x4 or x8 groups available on each side of your chosen device. Its the chosen memory device that specifys if x4 or x8 mode is required. If we assume that your DDR3 devices are x8 mode 16bit wide devices: EP4SGX230F1517's have 12 x8 groups on each side of the device. 12 x 8 = 96bits. But Remember that you will also require some additional pins for the CAC signals (Command Address and Clock). Also the Altera IP is currently limited to a maximum width of 80bits wide. So as each side of the EP4SGX230F1517 could in theory support a 96bit wide DDR3 interface (assuming enough spare pins are available for CAC), Then three 64bit wide DDR3 Interfaces, One on the Top, One on a Side, and one on the Bottom should be no problem.
