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Mahmoud353's avatar
Mahmoud353
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2 months ago

Max10M-16-SA-U-169 program without having the project file

Hi, I am trying to program the already designed and programmed Intel Max 10M-16-SA-U-169  to change the states of some of the components connecting to the FPGA. I do not have the project file and the pin assignment of the FPGA. I only have some .pof files that I can program the FPGA through the JTAG connection with a USB blaster. Is there any way to access the design of the FPGA through Quartus, or is there any way to do it with any other tools or software? Can I find out the pin assignment of the FPGA? I would appreciate it if anybody could help me with this situation.

Configuration

10 Replies

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi Mahmoud,

    Frank is correct, you can’t recover pin assignments from the bitstream, but with boundary-scan you can both observe and drive pin states by enabling outputs and setting values using tools like Quartus Programmer or TopJTAG. Just ensure you have the correct BSDL file and avoid driving against active outputs to prevent contention.

    Regards,
    Fakhrul

    • FakhrulA_altera's avatar
      FakhrulA_altera
      Icon for Regular Contributor rankRegular Contributor
      23 days ago

      Hi  Mahmoud353,

      Thanks for your response. I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

      Thank you for engaging with us!

      Best regards,
      Altera Technical Support

    • FakhrulA_altera's avatar
      FakhrulA_altera
      Icon for Regular Contributor rankRegular Contributor
      30 days ago

      Hi Mahmoud,

      I wish to follow up with you on this case. Do you still have further inquiries on this issue? Please feel free to let me know if there is any concern so that we could further assist you.
       

      Regards,
      Fakhrul

      • FakhrulA_altera's avatar
        FakhrulA_altera
        Icon for Regular Contributor rankRegular Contributor
        26 days ago

        Hi Mahmoud,
         

        Just checking in. Do you still have further inquiries on this issue? Please feel free to let me know if there is any concern so that we could further assist you.
         

        Regards,
        Fakhrul

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 months ago

    Hi, boundary scan logic allows also to change data direction (enable/disable tri-state drivers) and set output state of pins. You can e.g. read or write memory devices connected to FPGA pins. There are various BSDL tools available,  I'm e.g. using TopJTAG Probe with USB-Blaster and Altera FPGA.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 months ago

    Hi,

    retrieving pin configuration and netlist from configuration bitstream isn't supported by vendor provided or commonly available tools. Scientific papers demonstrated however basic feasibility for unencrypted configuration files.

    Data direction and state of IO-pins of configured FPGA can be observed in operation with boundary scan tool.

    Regards

    Frank

    • Mahmoud353's avatar
      Mahmoud353
      Icon for New Contributor rankNew Contributor
      2 months ago

      Thank you, Frank, for the response. With this method, only the state of the pins can be detected, so it cannot find the pin configuration. Another question is whether it is possible to change the state of the pins while they have been detected in this way?