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Altera_Forum's avatar
Altera_Forum
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8 years ago

MAX10/DE10-Lite clock skew issue

As a simple demo, I wrote verilog code for an updown counter on the DE10-Lite board using buttons, LEDs and switches. KEY[1] is used as clock and KEY[0] is used as synchronous reset. The counte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If you haven't done so, set a clock constraint like:

create_clock -name clk -period 1000 [ get_ports KEY[0] ] ; Constraining as a 1 MHz clock; TimeQuest can't (couldn't?) handle very low frequency clocks

Then run TimeQuest and see if the meets timing of if you have failing paths.