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Altera_Forum
Honored Contributor
8 years agoI'm using a 10M04DCF256 in a similar setup - no NIOS, just my own logic around the IP core. As it happens, my main clock is also 80MHz.
I didn't record the precise numbers, but for debugging I routed the signals of interest out to I/O pins and viewed them with a 'scope - the waitreq was going active for a reasonable amount of time, somewhere around the 100us specified in the manual. There are a number of minor errors in the documentation - the one which upset my state machine was the fact that waitreq also goes active during a read cycle (fig 10 in the manual says it doesn't!). On the write cycle, fig8 shows the waitreq going active on the same cycle as the write strobe - which is impossible unless there's asynchronous logic (or a time machine) inside the IP core. So, I agree you ought to be able to write your data in about 1 second. Probably something has gone wrong with your state machine....