New Contributor
Super ContributorIt is very likely that this is a timing issue. Looking quickly at your compilation report, your hold slack values are really small compared to your relatively gigantic setup slack values.
Looking at your .sdc file, is there a structure in your design that is performing divide by 2 on those 4 clocks after the PLL? If not, you don't need those 4 constraints because derive_pll_clocks already constrains the outputs of the PLL. Adding those extra constraints, assuming your PLL is already doing a divide by 2, means those clocks are now divide by 4 with respect to the input reference clock to the PLL. Or are these output clocks from the device? I'm guessing not because they're not targeting output ports of the device.
You're also missing set_input_delay and set_output_delay constraints for the I/O in your design, so your design is not fully constrained for timing. Check the unconstrained paths report to see what you need to constrain.
As for the warnings, counter_reg_bit, InsAdr, and MemLin are not shown in your code so it's not clear why those signals are being seen as clocks.
Finally, I don't know if it's part of the issue, but you have a lot of comparator logic in your SAM next state logic (3 levels at most). You might want to do those comparator checks in separate processes to simplify the next state logic.
Hope this helps a bit.
#iwork4intel
