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Altera_Forum
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8 years ago

MAX10 RSU unconstrained clocks

Hello, I'm getting two errors from the reconfiguration module in the MAX10 FPGA. I'm trying to use the dual_boot_cfg module and onchip_flash modules and am getting TimeQuest errors reporting uncon...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Do you have SDC constraints for the base clock(s) coming into the FPGA and any other generated clocks coming from, say, PLLs outside the system? Even though you shouldn't have to constrain clocks internal to a Qsys system, you still have to constrain what's outside the system.