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Altera_Forum
Honored Contributor
Honored ContributorMAX10 RSU unconstrained clocks
Hello, I'm getting two errors from the reconfiguration module in the MAX10 FPGA. I'm trying to use the dual_boot_cfg module and onchip_flash modules and am getting TimeQuest errors reporting uncon...
Altera_ForumHonored Contributor
Honored ContributorDo you have SDC constraints for the base clock(s) coming into the FPGA and any other generated clocks coming from, say, PLLs outside the system? Even though you shouldn't have to constrain clocks internal to a Qsys system, you still have to constrain what's outside the system.
