MAX10 RSU Project

As mentioned, Avalon masters use byte addressing and Avalon slaves use word addressing. The word size is typically the data width (32 in this case). So Avalon masters access the registers/memory locations for a slave at addresses 0x0, 0x4, 0x8, etc. For a 16 bit slave, the master would access the slave at 0x0, 0x2, 0x4, etc., though if the master itself is 32-bit, it would only need to access at 0x0, 0x4, etc. and could use byte enables for the appropriate bytes/words. See the Avalon spec for details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

Also check out online training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html

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