MAX10 RSU Project

Why byte addressing? It says we writes words in ug-m10-ufm-16.0.pdf, so we create a word word = (receivedHex[0]<<24)|(receivedHex[1]<<16)|(receivedHex[2]<<8)|(receivedHex[3]); then write it to a specific address and then what? skip 4 addresses?

When I generate FLASH UPDATE IP in QSYS

component flash_update is

port (

clock : in std_logic := '0'; -- clk.clk

avmm_csr_addr : in std_logic := '0'; -- csr.address

avmm_csr_read : in std_logic := '0'; -- .read

avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata

avmm_csr_write : in std_logic := '0'; -- .write

avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata

avmm_data_addr : in std_logic_vector(18 downto 0) := (others => '0'); -- data.address

avmm_data_read : in std_logic := '0'; -- .read

avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata

avmm_data_write : in std_logic := '0'; -- .write

avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata

avmm_data_waitrequest : out std_logic; -- .waitrequest

avmm_data_readdatavalid : out std_logic; -- .readdatavalid

avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount

reset_n : in std_logic := '0' -- nreset.reset_n

);

end component;

as we can see data bus 32-bit and on every write I should increment avmm_data_addr by one as I understand.

When I create Altera On-Chip Flash IP I get the following addresses

sector 3 - 0x10000 - 0x6FFFF

sector 4 - 0x70000 - 0xB7FFF

sector 5 - 0xB8000 - 0x15FFFF

But when I Generate HDL

SECTOR3_START_ADDR => 16384,

SECTOR3_END_ADDR => 114687,

SECTOR4_START_ADDR => 114688,

SECTOR4_END_ADDR => 188415,

SECTOR5_START_ADDR => 188416,

SECTOR5_END_ADDR => 360447,

So it's already divided by 4. Isn't it?