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Altera_Forum
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8 years ago

MAX10 RAM (M9K) content at power up?

I am using MAX10 10M04DCF256. Documentation for the M9K RAM blocks makes clear that the output register of the RAM is cleared at power-up and you don't see RAM content at the output until after...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

All FPGA registers, including those in a RAM block unless initialized with a .hex or .mif file, power up low. This is common across all device families (though Stratix 10 does now allow you to power up a register to 1).