MAX10 primitive TRI-state output buffer ERROR

You can configure the 'Altera GPIO Lite' IP as a bidirectional buffer.

Cheers,

Alex

Alex, Thanks again for replying to my other posts. ..... I'm not sure what you are referring to here. Is this something that is in the primitive pin folder when you place a part? Some pins need to be bidirectional and some need to be able to be placed into HI-Z.

Thanks,

Keith

The 'Altera GPIO Lite' IP is available in Quartus from the IP Catalog. With your project open in Quartus, make sure you can see the IP Catalog (press ALT+7 to hide/show it). Type 'GPIO' in the search box to find it and double click it. You can then configure the IP (as the 'bidir' buffer you need) and instantiate it in your design. Use the rtl (Verilog or VHDL) or you can use the .bsf symbol file if you capturing with schematics.

Cheers,

Alex

Morning Alex,

OK, I guess I am not following what is going on. I can bring up my IP Catalog, but I can't find my ALT_OUTBUF_TRI to configure. I am doing a total schematic capture design. I also get an error that states that File extenstion (.bsf) is not supported for the IP variation files.

I guess my design of programming of a chip or 2 every 3-4 years is a big drawback of trying to learn new software with a steep learning curve. Kindof why I liked 9.0 since it was simple, and had an integrated simulator, (without having to create a new project and then go find your .v?? file)

Since my designs are simple I thought it should be a fairly easy:

1) load the original project (schematic)

2) reconfig for new device

3) recompile

4) test timing-waveform

5) layout new pin locations

6) done.....

Any other suggestions on what I am doing wrong? My designs are schematic based, no Verilog or VHDL.

Thanks,

Keith

This is what you are doing wrong:

--- Quote Start ---

Any other suggestions on what I am doing wrong? My designs are schematic based, no Verilog or VHDL.

--- Quote End ---

Spend time time to learn Verilog/SystemVerilog or VHDL, depending upon your preference or job requirements.

Doing current FPGA design using vendor schematic tools is a dead end. It also locks your design into that specific vendor's tool set.

I would not be surprised in a couple of years if the schematic tools were discontinued in favor of only supporting Verilog/VHDL/OpenCL languages.

--- Quote Start ---

I can bring up my IP Catalog, but I can't find my ALT_OUTBUF_TRI to configure

--- Quote End ---

It's not there any more - you're looking for the 'Altera GPIO Lite'.

There is a lot - yes, a lot - to be said for capturing your design in rtl. I (also) suggest you look into this. There are plenty of self help tutorials online. You wouldn't be struggling with this IP issue if your tri-state buffer was inferred in your code. Quartus would simply implement the appropriate buffer from whatever FPGA family you're targeting.

Cheers,

Alex