MAX10 primitive TRI-state output buffer ERROR

This is what you are doing wrong:

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Any other suggestions on what I am doing wrong? My designs are schematic based, no Verilog or VHDL.

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Spend time time to learn Verilog/SystemVerilog or VHDL, depending upon your preference or job requirements.

Doing current FPGA design using vendor schematic tools is a dead end. It also locks your design into that specific vendor's tool set.

I would not be surprised in a couple of years if the schematic tools were discontinued in favor of only supporting Verilog/VHDL/OpenCL languages.