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Altera_Forum
Honored Contributor
Honored ContributorMax10 PCB Layout - Unused Pins
Hello,
I am building my first from-scratch FPGA project. I’m using a Max10 10M02SC 153-MBGA, but my design is really simple. I really only need to use one bank because I only need about 16 I/Os. (I started with a smaller Max10, but I wanted the single-supply option to keep my PCB simpler.) I’m running everything at 3.3V, and I’m not using the ADC or anything else fancy. I don’t even have an external clock- I’m using the Max10’s built-in clock. I’ve tested the design on an evaluation board, and it does work. So, I am now going to have around 100 unused pins. I have read many places that I can set them to “inputs tri-stated with weak pull up” and then I don’t need to even connect them to the PCB. Is that correct? My big reason for asking is this: because my design is so simple, and low-speed (external clock speeds are about 14kHz), I would like to eliminate some of the MBGA pads to allow easier trace routing to other pads. This way I can keep the PCB to 2 layers and hopefully not need expensive laser-drilled microvias. Does this sound reasonable? I do intend to connect all of the VCCIO, VCC_ONE, VCCA, and GND pins, so there will still be a lot of mechanical stability. Thanks!13 Replies
Altera_ForumHi James,
So far, it has worked out pretty well. I never figured out why sending that signal to an I/O fixed the timing issue, but it seems like it did. I can use that signal for testing anyway. The internal oscillator works; just be careful because (as you probably noticed) the datasheet gives it a HUGE tolerance. It will save a little money on an external oscillator, but your design must be very tolerant of using different frequencies (mine is). I had another project take my focus, but we plan to return to it shortly and finish testing. However, in the tests we did run, everything seemed really good, thank God. I hope yours goes well! Robert- Altera_Forum
Hi Newtham,
Just curious how your design turned out? I'm starting an FGPA design with the MAX10 and was planning to use the internal oscillator. How did it work out for you? Thanks! James - Altera_Forum--- Quote Start --- Thanks Alex. Yeah, my PCB house has a minimum of 8 mils (0.2mm) for mechanically drilled vias. But I'm pretty sure I will still be able to fit that in between pads, as you suggest. We'll see how it goes. :) Thanks again --- Quote End --- I'm going to throw out that doing pad-in-via really depends on what exactly you're looking at doing. If the vias aren't filled, it is possible that you can get some very odd reflow leading to non-standard connections, but if the BGA has been designed for it, one should be okay. Otherwise you need to pay to get filled vias , depending.
- Altera_Forum
Thanks Alex.
Yeah, my PCB house has a minimum of 8 mils (0.2mm) for mechanically drilled vias. But I'm pretty sure I will still be able to fit that in between pads, as you suggest. We'll see how it goes. :) Thanks again - Altera_Forum--- Quote Start --- So how did you route this package without the microvias? --- Quote End --- I've (finally) managed to have a look over the job I mentioned. It was a Cyclone III device in a MBGA-164 package. It looks like I used a 0.2mm pad for the via with a 0.1mm drill. This, along with a 0.2mm PCB pad for the device ball, allowed me to place vias in the centre of 4 pads, as you would normally for a larger pitch BGA package. All this allowed for full vias through a 0.8mm thick 6 layer board. What PCB technology bracket this falls into will vary (a little) between vendors. My memory of it being a 'standard' tech is clearly not completely accurate. However, it can be manufactured and, I'm sure, will be cheaper than using microvias. Cheers, Alex
- Altera_Forum
I don't recall. You need to follow the PCG-01018 document. Some devices do allow open pins. Some don't.
- Altera_Forum
Right, ok. My design is pretty forgiving, so that might still work. But I will check it out.
If I do use the internal clock, can I just set the CLKn, CLKp, DPCLK, and PLL_CLK pins to weak pull up? Also for the CONFIG_SEL and CRC_ERROR pins (I'm programming with JTAG)? Thanks again, Robert - Altera_Forum
Newtham,
MAX10's internal clock is definitely nice, but if your logic depends on certain clock speed, you shouldn't use it. If your design can tolerate 55~116MHz variation, you are all good. Depending on the silicon batch(lot), one MAX10 generates 55Mhz, and other ones generate 116MHz. Once it runs at a clock frequency, it stays on that frequency which I've been told. However if you are building many boards, each board would have different clock speed depending on silicon batch(lot). If you have space on your board, use bigger footprint part. It costs more to build smaller, and it could get somewhat complicated. Regards, - Altera_Forum
Now I'm wondering: how accurate is the Max 10 internal oscillator? I think my design is very tolerant, but if the clock varies a lot, maybe I should think about something else.
I found a chart in the datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf) (p.28) that said the frequency was anywhere from 55-116MHz, typically 82MHz. For some reason I was thinking it was *either* 55 or 116, so I guess I'm reading that wrong...(?) Probably misunderstood the IP Editor's window. Thanks! - Altera_Forum
OK, thanks, Kevin.
Yes, I am already adding 10 spare I/Os, and I have seen the document you mentioned. Thanks for the info on the clock: I didn't realize that. However, I think I'll be OK in this case. After reviewing the BGA guidelines and my PCB house's specs again, it looks like I will be able to use 8 mil mechanically-drilled vias. I think I can squeeze these in between pads where I need them, so hopefully I won't need to eliminate any pads. Thanks for your good advice! Robert
