Max10 PCB Layout - Unused Pins

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I can set them to “inputs tri-stated with weak pull up” and then I don’t need to even connect them to the PCB. Is that correct?

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In this instance they need not be electrically connected. You're correct in that regard. However...

If I understand your post correctly you're proposing to remove PCB pads for device pads that are not used. Correct? In theory this is fine. However, I would anticipate you having difficulties assembling this. Without an associated pad for the MBGA ball to reflow to, I'd anticipate problems. What will this reflowed solder ball (from the package) do without a pad? Will it behave and solidify in situe or, without the expected reflow shape, will it end up shorting to another pin?

You may well find this is not an issue. Dropping a pad or two certainly wouldn't be an issue for traditional 'legged' devices and I suspect with larger pitch BGA devices you could well get away with this. Even if your unused input with pull-up does short to another pin - so what? As long as it only shorts to one other pin.

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keep the PCB to 2 layers and hopefully not need expensive laser-drilled microvias

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I strongly recommend you look to 4 layers for such a device. I've routed this package (although not MAX 10), on 6 layers, without the need for any micro-vias. You should be able to find a standard PCB technology that allows you to do all you need without the need to remove any pads.

Cheers,

Alex

Hi Alex,

Thank you very much. That's good info, which is what I need!

OK, since I have never routed a BGA before, I was looking at Altera's document on how to do it (an114 (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an114.pdf)). They seem to indicate that you must use in-pad vias, and, since the pads are so small, this means you must use microvias.

So how did you route this package without the microvias? Any tips you can give me wold be greatly appreciated!

Thanks again!

Robert

Any unused pin should be connected to PCB as a pad which doesn't route any where. This helps during assembly.

About the MAX10's clock, you might want to consider placing spare clock source as backup. MAX10's internal clock has big range of uncertainty. If your design doesn't care "exact time", then you will be okay. Another recommendation is to bring out test points on unused pins for debugging or for spare. It's just a practice. Lastly, review PCG-01018 document which is max10 fpga device family pin connection guidelines.

Regards,

Kevin

OK, thanks, Kevin.

Yes, I am already adding 10 spare I/Os, and I have seen the document you mentioned. Thanks for the info on the clock: I didn't realize that. However, I think I'll be OK in this case.

After reviewing the BGA guidelines and my PCB house's specs again, it looks like I will be able to use 8 mil mechanically-drilled vias. I think I can squeeze these in between pads where I need them, so hopefully I won't need to eliminate any pads.

Thanks for your good advice!

Robert

Now I'm wondering: how accurate is the Max 10 internal oscillator? I think my design is very tolerant, but if the clock varies a lot, maybe I should think about something else.

I found a chart in the datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf) (p.28) that said the frequency was anywhere from 55-116MHz, typically 82MHz. For some reason I was thinking it was *either* 55 or 116, so I guess I'm reading that wrong...(?) Probably misunderstood the IP Editor's window.

Thanks!

Newtham,

MAX10's internal clock is definitely nice, but if your logic depends on certain clock speed, you shouldn't use it. If your design can tolerate 55~116MHz variation, you are all good. Depending on the silicon batch(lot), one MAX10 generates 55Mhz, and other ones generate 116MHz. Once it runs at a clock frequency, it stays on that frequency which I've been told. However if you are building many boards, each board would have different clock speed depending on silicon batch(lot).

If you have space on your board, use bigger footprint part. It costs more to build smaller, and it could get somewhat complicated.

Regards,

Right, ok. My design is pretty forgiving, so that might still work. But I will check it out.

If I do use the internal clock, can I just set the CLKn, CLKp, DPCLK, and PLL_CLK pins to weak pull up? Also for the CONFIG_SEL and CRC_ERROR pins (I'm programming with JTAG)?

Thanks again,

Robert

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So how did you route this package without the microvias?

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I've (finally) managed to have a look over the job I mentioned. It was a Cyclone III device in a MBGA-164 package. It looks like I used a 0.2mm pad for the via with a 0.1mm drill. This, along with a 0.2mm PCB pad for the device ball, allowed me to place vias in the centre of 4 pads, as you would normally for a larger pitch BGA package. All this allowed for full vias through a 0.8mm thick 6 layer board.

What PCB technology bracket this falls into will vary (a little) between vendors. My memory of it being a 'standard' tech is clearly not completely accurate. However, it can be manufactured and, I'm sure, will be cheaper than using microvias.

Cheers,

Alex

Thanks Alex.

Yeah, my PCB house has a minimum of 8 mils (0.2mm) for mechanically drilled vias. But I'm pretty sure I will still be able to fit that in between pads, as you suggest.

We'll see how it goes. :)

Thanks again