FrankK
New Contributor
New ContributorMAX10 nCONFIG pin slew rate requirement
Hello, is there any requirement for nCONFIG pin of MAX10 family with regards to signal transition time (signal slew rate)? Unfortunately MAX10 data sheet does not include any parameter for the same....
Hi FrankK,
To answer your question, Altera does not publish a slew‑rate spec for nCONFIG in the MAX 10 datasheet. Refer MAX 10 FPGA Device Datasheet
- During configuration, MAX 10 uses Schmitt‑trigger input buffers by default, so slow or noisy edges are tolerated. MAX 10 FPGA Signal Integrity Design Guidelines
- Schmitt input hysteresis is about 180 mV at 3.3 V, 150 mV at 2.5 V, 120 mV at 1.8 V, 110 mV at 1.5 V. Check here https://docs.altera.com/r/docs/683794/current/max-10-fpga-device-datasheet/hysteresis-specifications-for-schmitt-trigger-input
- To force reconfiguration, keep nCONFIG low at least 2 µs. https://community.altera.com/kb/knowledge-base/what-are-the-minimum-nconfig-low-pulse-width-and-the-maximum-nstatus-low-pulse-w/347246
- Connect nCONFIG high on power‑up, typically with a 10 kΩ pull‑up to VCCIO. Refer MAX 10 FPGA Device Family Pin Connection Guidelines
- Holding nCONFIG low to delay configuration does not relax the POR ramp‑time requirements. Try refer Possibility to avoid configuration power requirements for single-supply MAX10 by using nconfig
In practice, use a clean, monotonic nCONFIG edge and keep noise away from the threshold region. The Schmitt buffer helps, but clean edges are still best. MAX 10 FPGA Signal Integrity Design Guidelines
Regards,
Fakhrul
