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avign1's avatar
avign1
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7 years ago
Solved

Max10 JTAG programming from SVF

I have a custom board with an 10M50SC connected to an FTDI 4232H. I wrote the necessary software to program it using the SVF files produced by Quartus 18.1. Everything works fine (albeit quite slowly...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi avign1,

The PULSE_NCONFIG is to emulate the nCONFIG pin function to trigger internal re-configuration during user mode (after the 1st internal configuration). This command does not work to force the CFM memory block to perform internal configuration (after the .pof programming) to CRAM without power cycle. You can refer to the following link for the JTAG instruction to force CRAM download from CFM memory block after ISP programming withou power cycle:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd06202005_565.html

Regards,

Nooraini

avign1's avatar
avign1
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7 years ago

Yes, it works. Thank you.

I already found another solution: paste the ending lines from the SVF "SOF" file just before the last BYPASS instruction. They perform a 1500-bit boundary scan to check the state of the CONF_DONE pin, using the undocumented opcode 0x04 instead of the standard 0x05. It seems that this boundary scan (with 0x04 or 0x05) followed by the other undocumented opcode 0x03 is able to start the reconfiguration.