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OK - the decision to use MAX 10 is fine, it can be a fine solution. However, I maintain that supporting an upgrade path in the field, via JTAG, is shortsighted. The lack of documentation in this respect should be ringing alarm bells.
So you need to maintain this path for the purposes of manufacturing. Why over complicate it by also giving the micro access to the same JTAG nets? You will be mightily frustrated should your prototype come back and JTAG doesn't work because you've over complicated access to, and compromised, those nets.
So you do have another route into the MAX 10 FPGA(s). Upgrade the MAX 10 FLASH via this route and leave JTAG available for manufacturing and development.
See the
max 10 fpgas bsdl files (
https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/max-10.html) page for the relevant BSDL file. However, you will NOT be able to reverse engineer the FPGA programming from this. This file describes the FPGA's I/O cells and the registers that can be accessed via JTAG. It will not tell you how to use them or how to program the FPGA.
If you really,
really, REALLY must use JTAG then you should consider reverse engineering a Serial Vector File (SVF), which you can generate from Quartus -
see here (
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07222008_677.html). These files are what a manufacturer is likely to use to program up and FPGA, via JTAG, using their own JTAG equipment.
However, I still maintain the best route for upgrading MAX 10 FLASH, in the field, is via your micro<->FPGA interface, not JTAG.
Good luck with your development.
Cheers,
Alex
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Hi Alex,
I am trying to generate SVF file for MAX10 from Quartus but I found that those options under Device and Pin Options -> Programming Files has been shaded out.
Do you face this issue before?
Regards,
Soo Cheng
Honored Contributor
