Forum Discussion

David_Ben_Hamou's avatar
David_Ben_Hamou
Icon for New Contributor rankNew Contributor
5 years ago

MAX10 i/o state during Device Initialization (before user mode and after configuration time)

Good afternoon, I have my output pins during the device initialization phase which has a level of 1.2V (3.3V I/O power Bank) and I have 10K pull down on my output signal (LVCMOS 3.3V). I don't know...
David_Ben_Hamou's avatar
David_Ben_Hamou
Icon for New Contributor rankNew Contributor
5 years ago

Hello,

Thanks for the reply.

I need more information about the following point:

During initialization mode, internal logic and I/O registers are initialized and I/O buffers are enabled.

What is the behavior of I/O pins of the FPGA during this phase ('Z' or wealky pull-up or something different) ?

Thanks