MAX10 IBIS model- stair stepping

Hello,

Thank you for informing us about this issue you are facing.

Is it okay if you share with steps you have done to reproduce the table in the snapshot?

Or else share with us the file?

It will help me to further investigate this.

Regards,

Aqid

Hi,

I would like to follow up with you regarding this issue.

May I know if you have any updates on my last questions for clarification?

Regards,

Aqid

After reviewing the Power clamp response, we identified stair-stepping in the IV curve by checking curve visually . Would you be able to clarify the reason behind this occurrence?

any update???. It is a bit urgent

Hi,

Apologies for the late reply as I am having a little bit delay in confirmation from the internal team. However, the latest discussion has found out that the HSPICE models is showing the correct behavior across different corners in the power clamp table.

The internal team is going to verify if how much impact of the stair stepping power clamp to the transient simulation and early assumption is the power clamp is not having significant impact on the board simulation because the leakage is very small which in unit of uA.

In the meantime, can you confirm that you using this particular model as the output buffer? And is it okay for you to use the HSPICE models instead to continue with the board simulation?

Regards,

Aqid

Hello Aqid,

We are indeed utilizing this specific model for input and output configuration. If the current present in the power clamp table is leakage current, how will this pin clamp if I connect a voltage beyond VCC? Therefore, my inquiry is whether this pin contains a power clamp diode. Additionally, our tool does not support HSPICE model for simulation.

Regards,

Shweta

Hi Shweta,

Max 10 does support the PCI Clamp Diode, as what I found in the Max 10 GPIO User Guide:

https://www.intel.com/content/www/us/en/docs/programmable/683751/22-1/pci-clamp-diode.html

There are also mentioned that if you are using the I/O standard with a higher voltage than the VCCIO of the I/O bank, you have to enable the clamp diode. Refer here:

https://www.intel.com/content/www/us/en/docs/programmable/683751/22-1/guidelines-enable-clamp-diode-for-lvttl.html

For your information, the IBIS model's name with "_p" has the clamp diode enabled.

Regards,

Aqid

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.