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Shweta_sawant's avatar
Shweta_sawant
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

MAX10 IBIS model- stair stepping

I am using MAX10 IBIS model from that model- lvttl_rio_d4s2 in this model the power clamp table exhibits stair-stepping . According to IBIS specification ,There should be no stair stepping of any I...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi,


Apologies for the late reply as I am having a little bit delay in confirmation from the internal team. However, the latest discussion has found out that the HSPICE models is showing the correct behavior across different corners in the power clamp table.


The internal team is going to verify if how much impact of the stair stepping power clamp to the transient simulation and early assumption is the power clamp is not having significant impact on the board simulation because the leakage is very small which in unit of uA.


In the meantime, can you confirm that you using this particular model as the output buffer? And is it okay for you to use the HSPICE models instead to continue with the board simulation?


Regards,

Aqid