Forum Discussion
FvM
Super Contributor
7 hours agoHi,
did you try to reduce JTAG frequency of USB Blaster II in Programmer Hardware Setup? If this doesn't help, there may be a problem of TCK signal quality with your PCB design, causing crosstalk of other clock signals or ringing TCK edges. A small capacitive load (10 - 20 pF) at TCK near FPGA can help in some cases.
Regards
Frank