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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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Max10 Dual configuration IP read boot source

I am implementing RSU for a Max10M50 using discrete logic. I have components in place to read and write to CFM1&2 through a serial interface. I have instantiated the Dual Boot IP core hoping to be able to detect the image that got loaded on the current start up, but I don't see much regarding that in the MAX10 Configuration User Guide.

Basically, I want to be able to detect a boot from CFM1&2(the update image) so I can proceed as normal, or detect a boot from CFM0(factory image) prompt for a redownload. The only registers in the Dual Boot IP that may do this are offset 5 and 6, but this is not very clear to me. Which offset/bits should I be reading from to detect what image the current boot is running from?

  • DavidLarochelle's avatar
    DavidLarochelle
    4 years ago

    In ug_m10_config.pdf, section " Dual Configuration Intel FPGA IP Core References", you will see that

    - config_sel register allows you to select which CFM will be used for next boot

    - msm_cs register tells you which CFM was used on last boot

    Table 14 gives you de definition of the msm_cs register. I currently use the msm_cs from offset 4 and it seems to work as expected.

4 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    It's been a while since I've looked at this, but the CONFIG_SEL pin is used to select which image to use on boot (0=CFM0, 1=CFM1/2). Do you have no way of knowing what that signal is set to?

  • rt52's avatar
    rt52
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    While I can read the CONFIG_SEL pin, it is pulled up to always boot from CFM1/2, which is what I want under normal circumstances. However, in the case that something goes wrong with the image in CFM1/2, I need a way to see a boot has occurred from CFM0 so I can lock functionality and prompt for a redownload to CFM1/2. Unless I'm mistaken, I don't think the CONFIG_SEL pin changes to reflect that if it is on a 10K pull up

  • DavidLarochelle's avatar
    DavidLarochelle
    Icon for New Contributor rankNew Contributor
    4 years ago

    In ug_m10_config.pdf, section " Dual Configuration Intel FPGA IP Core References", you will see that

    - config_sel register allows you to select which CFM will be used for next boot

    - msm_cs register tells you which CFM was used on last boot

    Table 14 gives you de definition of the msm_cs register. I currently use the msm_cs from offset 4 and it seems to work as expected.

    • rt52's avatar
      rt52
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Thank you, yes that is what I was looking for.