MAX10 DDR3 Timing

Hi Adzim,

Unfortunately, the problem has not been resolved even with the references to the manuals on timing. An AI analysis of the failing DDR3 timings states:
"This is not a 'real' logic timing error but rather a classic DDR-DQS analysis artifact in the MAX10."

This is justified based on the following three points:

1️⃣ DQS is treated as a normal clock
Quartus interprets:
"A normal register is clocked by a normal clock (mem_dqs_l_n_OUT)"
❌ This is incorrect for DDR.
In reality:

• DQS is not a global clock.
• DQS is a source-synchronous strobe.
• Capture happens in the I/O element, not in the core logic.
  👉 Timing between pll_clk → mem_dq → dqs is physically coupled but not logically synchronized.

2️⃣ The clock skew is absurdly high (6.891 ns)
This is the second major red flag 🚨:

• Clock Skew: 6.891 ns
• Setup Relationship: 0.833 ns
  ➡️ Quartus compares:
  • PLL clock in the core
  • Against DQS, which comes from an I/O path.
    This has no real significance for DDR reads.

3️⃣ PLL compensation appears negative

• PLL Compensation: -7.957 ns / -8.063 ns
  This is typical for:
  • Generated clocks
  • DDR IP
  • DQS paths
    ➡️ The timing engine is being used outside its optimal range.

Can we use these statements to arrive at a solution?