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Altera_Forum
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8 years ago

MAX10 constraining IO problems

Hello, I am fairly new to FPGA development and learning about constraining my system but am really struggling. My system 'works' at certain clock frequencies but change something and I have I/O gl...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hello,

Ok, I uploaded a PNG which seems to have been converted to a JPG thumbnail by the forum software.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14400

It is a confusing situation for a novice because all data and clock lines are buffered so there are delays on everything and I know I don't understand yet how to enter all the delays & external device setup/hold timings correctly in an SDC file.

Thanks, I will go through that training.

I have also discovered another Rysc tutorial on source synchronous connections which I am reading. http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest